ST STM32F405 Reference Manual page 499

Hide thumbs Also See for STM32F405:

Table of Contents

LTDC Interrupt Status Register (LTDC_ISR)

This register returns the interrupt status flag

Address offset: 0x38

Reset value: 0x0000 0000

Bits 31:24 Reserved, must be kept at reset value

Bit 3 RRIF: Register Reload Interrupt Flag

Bit 2 TERRIF: Transfer Error interrupt flag

Bit 1 FUIF: FIFO Underrun Interrupt flag

Bit 0 LIF: Line Interrupt flag

LTDC Interrupt Clear Register (LTDC_ICR)

Address offset: 0x3C

Reset value: 0x0000 0000

0: No Register Reload interrupt generated

1: Register Reload interrupt generated when a vertical blanking reload occurs (and the

first line after the active area is reached)

0: No Transfer Error interrupt generated

1: Transfer Error interrupt generated when a Bus error occurs

0: NO FIFO Underrun interrupt generated.

1: A FIFO underrun interrupt is generated, if one of the layer FIFOs is empty and pixel

data is read from the FIFO

0: No Line interrupt generated

1: A Line interrupt is generated, when a programmed line is reached

RM0090 Rev 18

LCD-TFT controller (LTDC)

CRRIF CTERRIF CFUIF

Chapters

Table of Contents