Figure 254. Txe/Rxne/Bsy Behavior In Slave / Full-Duplex Mode; Rxonly=0) In Case Of Continuous Transfers - ST STM32F405 Reference Manual

Serial peripheral interface (SPI)
Figure 254. TXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0,
Example in Slave mode with CPOL=1, CPHA=1
SCK
MISO/MOSI (out)
TXE flag
Tx buffer
(write to SPI_DR)
BSY flag
MISO/MOSI (in)
RXNE flag
Rx buffer
(read from SPI_DR)
software software waits
writes 0xF1 until TXE=1 and
into SPI_DR writes 0xF2 into
SPI_DR
Transmit-only procedure (BIDIMODE=0 RXONLY=0)
In this mode, the procedure can be reduced as described below and the BSY bit can be
used to wait until the completion of the transmission (see
1. Enable the SPI by setting the SPE bit to 1.
2. Write the first data item to send into the SPI_DR register (this clears the TXE bit).
3. Wait until TXE=1 and write the next data item to be transmitted. Repeat this step for
each data item to be transmitted.
4. After writing the last data item into the SPI_DR register, wait until TXE=1, then wait until
BSY=0, this indicates that the transmission of the last data is complete.
This procedure can be also implemented using dedicated interrupt subroutines launched at
each rising edge of the TXE flag.
Note: During discontinuous communications, there is a 2 APB clock period delay between the
write operation to SPI_DR and the BSY bit setting. As a consequence, in transmit-only
mode, it is mandatory to wait first until TXE is set and then until BSY is cleared after writing
the last data.
After transmitting two data items in transmit-only mode, the OVR flag is set in the SPI_SR
register since the received data are never read.
888/1749

RXONLY=0) in case of continuous transfers

DATA 1 = 0xF1
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
set by hardware
cleared by software
0xF1 0xF2
set by cleared by software
DATA 1 = 0xA1
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
set by hardware
software waits
until RXNE=1 until TXE=1 and
and reads 0xA1 writes 0xF3 into
from SPI_DR
DATA 2 = 0xF2
set by hardware
cleared by software
0xF3
DATA 2 = 0xA2
cleared by software
0xA1
software waits software waits
until RXNE=1
and reads 0xA2
SPI_DR from SPI_ DR
RM0090 Rev 18
DATA 3 = 0xF3
set by hardware
DATA 3 = 0xA3
0xA2
software waits
until RXNE=1
and reads 0xA3
from SPI_DR
Figure 255 and Figure
RM0090
reset by hardware
0xA3
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256).