ST STM32F405 Reference Manual page 823

RM0090
26.6.5 RTC prescaler register (RTC_PRER)
Address offset: 0x10
Backup domain reset value: 0x007F 00FF
System reset: not affected
31 30 29
15 14 13
Res.
rw rw
Bits 31:24 Reserved
Bit 23 Reserved, must be kept at reset value.
Bits 22:16 PREDIV_A[6:0]: Asynchronous prescaler factor
Bit 15 Reserved, must be kept at reset value.
Bits 14:0 PREDIV_S[14:0]: Synchronous prescaler factor
Note: This register must be written in initialization mode only. The initialization must be performed
in two separate write accesses. Refer to
page 804
This register is write protected. The write access procedure is described in
write protection on page
26.6.6 RTC wakeup timer register (RTC_WUTR)
Address offset: 0x14
Backup domain reset value: 0x0000 FFFF
System reset: not affected
31 30 29
15 14 13
rw rw rw
28 27 26 25
Reserved
12 11 10 9
rw rw rw rw
This is the asynchronous division factor:
ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)
This is the synchronous division factor:
ck_spre frequency = ck_apre frequency/(PREDIV_S+1)
803.
28 27 26 25
12 11 10 9
rw rw rw rw
24 23 22
rw
8 7 6
PREDIV_S[14:0]
rw rw rw
Calendar initialization and configuration on
24 23 22
Reserved
8 7 6
WUT[15:0]
rw rw rw
RM0090 Rev 18
Real-time clock (RTC)
21 20 19 18
PREDIV_A[6:0]
rw rw rw rw
5 4 3 2
rw rw rw rw
RTC register
21 20 19 18
5 4 3 2
rw rw rw rw
17 16
rw rw
1 0
rw rw
17 16
1 0
rw rw
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