Syscfg External Interrupt Configuration Register 4; (Syscfg_Exticr4) - ST STM32F405 Reference Manual

RM0090
9.2.6

SYSCFG external interrupt configuration register 4

(SYSCFG_EXTICR4)

Address offset: 0x14
Reset value: 0x0000 0000
31 30 29
15 14 13
EXTI15[3:0]
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Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 12 to 15)
9.2.7 Compensation cell control register (SYSCFG_CMPCR)
Address offset: 0x20
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Reserved
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 READY: Compensation cell ready flag
Bits 7:2 Reserved, must be kept at reset value.
Bit 0 CMP_PD: Compensation cell power-down
28 27 26 25
12 11 10 9
EXTI14[3:0]
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These bits are written by software to select the source input for the EXTIx external
interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
0111: PH[x] pin
Note: PI[15:12] are not used.
27 26 25
11 10 9
0: I/O compensation cell not ready
1: O compensation cell ready
0: I/O compensation cell power-down mode
1: I/O compensation cell enabled
System configuration controller (SYSCFG)
24 23 22
Reserved
8 7 6
EXTI13[3:0]
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24 23 22
Reserved
8 7 6
READY
r
RM0090 Rev 18
21 20 19 18
5 4 3 2
EXTI12[3:0]
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21 20 19 18
5 4 3 2
Reserved
17 16
1 0
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17 16
1 0
CMP_PD
rw
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