Rcc Backup Domain Control Register (Rcc_Bdcr) - ST STM32F405 Reference Manual

RM0090
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM8LPEN: TIM8 clock enable during Sleep mode
Bit 0 TIM1LPEN: TIM1 clock enable during Sleep mode
6.3.20

RCC Backup domain control register (RCC_BDCR)

Address offset: 0x70
Reset value: 0x0000 0000, reset by Backup domain reset.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
The LSEON, LSEBYP, RTCSEL and RTCEN bits in the
register (RCC_BDCR)
write-protected and the DBP bit in the
STM32F42xxx and STM32F43xxx
Section 6.1.1: System reset on page 150
after a Backup domain Reset (see
external Reset will not have any effect on these bits.
31 30 29
15 14 13
RTCEN
Reserved
rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 BDRST: Backup domain software reset
Note: The BKPSRAM is not affected by this reset, the only way of resetting the BKPSRAM is
Bit 15 RTCEN: RTC clock enable
Bits 14:10 Reserved, must be kept at reset value.
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
This bit is set and cleared by software.
0: TIM8 clock disabled during Sleep mode
1: TIM8 clock enabled during Sleep mode
This bit is set and cleared by software.
0: TIM1 clock disabled during Sleep mode
1: TIM1 clock enabled during Sleep mode
are in the Backup domain. As a result, after Reset, these bits are
28 27 26 25
12 11 10 9
RTCSEL[1:0]
rw
This bit is set and cleared by software.
0: Reset not activated
1: Resets the entire Backup domain
through the Flash interface when a protection level change from level 1 to level 0 is
requested.
This bit is set and cleared by software.
0: RTC clock disabled
1: RTC clock enabled
PWR power control register (PWR_CR) for
has to be set before these can be modified. Refer to
for further information. These bits are only reset
Section 6.1.3: Backup domain
24 23 22
Reserved
8 7 6
Reserved
rw
RM0090 Rev 18
RCC Backup domain control
reset). Any internal or
21 20 19 18
5 4 3 2
LSEBY
P
rw
17 16
BDRST
rw
1 0
LSERD
LSEON
Y
r rw
199/1749
212