Watchdog Clock; Clock-Out Capability; Internal/External Clock Measurement Using Tim5/Tim11 - ST STM32F405 Reference Manual

Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
Note: To read the RTC calendar register when the APB1 clock frequency is less than seven times
the RTC clock frequency (f
date registers twice. The data are correct if the second read access to RTC_TR gives the
same result than the first one. Otherwise a third read access must be performed.
6.2.9

Watchdog clock

If the independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.
6.2.10

Clock-out capability

Two microcontroller clock output (MCO) pins are available:
•
MCO1
You can output four different clock sources onto the MCO1 pin (PA8) using the
configurable prescaler (from 1 to 5):
–
–
–
–
The desired clock source is selected using the MCO1PRE[2:0] and MCO1[1:0] bits in
the
•
MCO2
You can output four different clock sources onto the MCO2 pin (PC9) using the
configurable prescaler (from 1 to 5):
–
–
–
–
The desired clock source is selected using the MCO2PRE[2:0] and MCO2 bits in the
RCC clock configuration register
For the different MCO pins, the corresponding GPIO port has to be programmed in alternate
function mode.
The selected clock to output onto MCO must not exceed 100 MHz (the maximum I/O
speed).
6.2.11

Internal/external clock measurement using TIM5/TIM11

It is possible to indirectly measure the frequencies of all on-board clock source generators
by means of the input capture of TIM5 channel4 and TIM11 channel1 as shown in
and Figure
Internal/external clock measurement using TIM5 channel4
TIM5 has an input multiplexer which allows choosing whether the input capture is triggered
by the I/O or by an internal clock. This selection is performed through the TI4_RMP [1:0] bits
in the TIM5_OR register.
158/1749
APB1
HSI clock
LSE clock
HSE clock
PLL clock
RCC clock configuration register
HSE clock
PLL clock
System clock (SYSCLK)
PLLI2S clock
19.
< 7xf ), the software must read the calendar time and
RTCLCK
(RCC_CFGR).
(RCC_CFGR).
RM0090 Rev 18
RM0090
Figure 18