Figure 102. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36; Figure 103. Counter Timing Diagram, Internal Clock Divided By N - ST STM32F405 Reference Manual

Advanced-control timers (TIM1 and TIM8)

Figure 102. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

Timerclock = CK_CNT
Update event (UEV)
Update interrupt flag (UIF)
1. Center-aligned mode 2 or 3 is used with an UIF on overflow.
528/1749
CK_PSC
CNT_EN
Counter register
Counter overflow

Figure 103. Counter timing diagram, internal clock divided by N

CK_PSC
Timerclock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
0034 0035
20 1F
RM0090 Rev 18
0036
01 00
RM0090
0035
MS31191V2
MS31192V2