ST STM32F405 Reference Manual page 427

RM0090
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 OVR1: Overrun flag of ADC1
Bit 4 STRT1: Regular channel Start flag of ADC1
Bit 3 JSTRT1: Injected channel Start flag of ADC1
Bit 2 JEOC1: Injected channel end of conversion of ADC1
Bit 1 EOC1: End of conversion of ADC1
Bit 0 AWD1: Analog watchdog flag of ADC1
13.13.16 ADC common control register (ADC_CCR)
Address offset: 0x04 (this offset address is relative to ADC1 base address + 0x300)
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
DMA[1:0] DDS
Res.
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Bits 31:24 Reserved, must be kept at reset value.
Bit 23 TSVREFE: Temperature sensor and V
Note: On STM32F42x and STM32F43x devices, VBATE must be disabled when TSVREFE is
Bit 22 VBATE: V
Bits 21:18 Reserved, must be kept at reset value.
This bit is a copy of the OVR bit in the ADC1_SR register.
This bit is a copy of the STRT bit in the ADC1_SR register.
This bit is a copy of the JSTRT bit in the ADC1_SR register.
This bit is a copy of the JEOC bit in the ADC1_SR register.
This bit is a copy of the EOC bit in the ADC1_SR register.
This bit is a copy of the AWD bit in the ADC1_SR register.
27 26 25
Reserved
11 10 9
DELAY[3:0]
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This bit is set and cleared by software to enable/disable the temperature sensor and the
V channel.
REFINT
0: Temperature sensor and V
1: Temperature sensor and V
set. If both bits are set, only the VBAT conversion is performed.
enable
BAT
This bit is set and cleared by software to enable/disable the V
0: V channel disabled
BAT
1: V channel enabled
BAT
24 23 22
TSVREFE VBATE
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8 7 6
Reserved
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enable
REFINT
channel disabled
REFINT
channel enabled
REFINT
RM0090 Rev 18
Analog-to-digital converter (ADC)
21 20 19 18
Reserved
5 4 3 2
MULTI[4:0]
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channel.
BAT
17 16
ADCPRE
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1 0
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