ST STM32F405 Reference Manual page 196

Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
Bit 3 TIM5LPEN: TIM5 clock enable during Sleep mode
Bit 2 TIM4LPEN: TIM4 clock enable during Sleep mode
Bit 1 TIM3LPEN: TIM3 clock enable during Sleep mode
Bit 0
196/1749
This bit is set and cleared by software.
0: TIM5 clock disabled during Sleep mode
1: TIM5 clock enabled during Sleep mode
This bit is set and cleared by software.
0: TIM4 clock disabled during Sleep mode
1: TIM4 clock enabled during Sleep mode
This bit is set and cleared by software.
0: TIM3 clock disabled during Sleep mode
1: TIM3 clock enabled during Sleep mode
TIM2LPEN: TIM2 clock enable during Sleep mode
This bit is set and cleared by software.
0: TIM2 clock disabled during Sleep mode
1: TIM2 clock enabled during Sleep mode
RM0090 Rev 18
RM0090