Figure 173. Control Circuit In External Clock Mode 2 + Trigger Mode; Figure 174. Master/Slave Timer Example - ST STM32F405 Reference Manual

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Counter clock = CK_CNT = CK_PSC

Timer synchronization

The TIMx timers are linked together internally for timer synchronization or chaining. When

one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of

another Timer configured in Slave Mode.

The clock of the slave timer must be enabled prior to receiving events from the master timer,

and must not be changed on-the-fly while triggers are received from the master timer.

Using one timer as prescaler for another timer

Figure 173. Control circuit in external clock mode 2 + trigger mode

Counter register

presents an overview of the trigger selection and the master mode selection

General-purpose timers (TIM2 to TIM5)

Input trigger

RM0090 Rev 18

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