Table 30. Standby Mode Entry And Exit - ST STM32F405 Reference Manual

RM0090
Entering Standby mode
The Standby mode is entered according to
SLEEPDEEP bit in the Cortex
Refer to
In Standby mode, the following features can be selected by programming individual control
bits:
•
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a reset. See
Section 21.3
•
Real-time clock (RTC): this is configured by the RTCEN bit in the backup domain
control register (RCC_BDCR)
•
Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
•
External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
backup domain control register (RCC_BDCR)
Exiting Standby mode
The Standby mode is exited according to
flag in PWR_CR (see
STM32F405xx/07xx and
mode. All registers are reset after wakeup from Standby except for PWR_CR.
Refer to
Standby mode
Mode entry
Mode exit
Wakeup latency
®
Table 30 for more details on how to enter Standby mode.
in Section 21: Independent watchdog
Section 5.4.2: PWR power control/status register (PWR_CSR) for
STM32F415xx/17xx) indicates that the MCU was in Standby
Table 30 for more details on how to exit Standby mode.

Table 30. Standby mode entry and exit

WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP is set in Cortex
– PDDS bit is set in Power Control register (PWR_CR),
– No interrupt (for WFI) or event (for WFE) is pending,
– WUF bit is cleared in Power Control register (PWR_CR),
– the RTC flag corresponding to the chosen wakeup source (RTC Alarm A,
RTC Alarm B, RTC wakeup, Tamper or Timestamp flags) is cleared
On return from ISR while:
– SLEEPDEEP bit is set in Cortex
and
– SLEEPONEXIT = 1, and
– PDDS bit is set in Power Control register (PWR_CR), and
– No interrupt is pending,
– WUF bit is cleared in Power Control/Status register (PWR_SR),
– The RTC flag corresponding to the chosen wakeup source (RTC Alarm
A, RTC Alarm B, RTC wakeup, Tamper or Timestamp flags) is cleared.
WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
tamper event, time stamp event, external reset in NRST pin, IWDG reset.
Reset phase.
Section : Entering low-power
-M4 with FPU System Control register is set.
Section : Exiting low-power
Description
®
RM0090 Rev 18
Power controller (PWR)
mode, when the
(IWDG).
mode. The SBF status
-M4 with FPU System Control register,
®
-M4 with FPU System Control register,
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