Embedded Flash Memory In Stm32F405Xx/07Xx And Stm32F415Xx/17Xx; Figure 4. Flash Memory Interface Connection Inside System Architecture (Stm32F42Xxx And Stm32F43Xxx) - ST STM32F405 Reference Manual

Embedded Flash memory interface
Figure 4. Flash memory interface connection inside system architecture
Cortex-M4 with FPU
Cortex
core
3.3 Embedded Flash memory in
STM32F405xx/07xx and STM32F415xx/17xx
The Flash memory has the following main features:
•
Capacity up to 1 Mbyte
•
128 bits wide data read
•
Byte, half-word, word and double word write
•
Sector and mass erase
•
Memory organization
The Flash memory is organized as follows:
–
–
–
–
•
Low-power modes (for details refer to the Power control (PWR) section of the reference
manual)
74/1749
(STM32F42xxx and STM32F43xxx)
I-Code
I-Code bus
D-Code
S bus
D-code bus
CCM data
RAM
DMA1
DMA2
DMA2D
LCD-TFT
USB HS
Ethernet
Access to instruction in Flash memory
Access to data and literal pool in Flash memory
FLITF register access
A main memory block divided into 4 sectors of 16 Kbytes, 1 sector of 64 Kbytes,
and 7 sectors of 128 Kbytes
System memory from which the device boots in System memory boot mode
512 OTP (one-time programmable) bytes for user data
The OTP area contains 16 additional bytes used to lock the corresponding OTP
data block.
Option bytes to configure read and write protection, BOR level, watchdog
software/hardware and reset when the device is in Standby or Stop mode.
AHB
32-bit
instruction
bus
AHB
32-bit
data bus
AHB
32-bit
system bus
RM0090 Rev 18
Flash
memory
Flash interface
bus
128 bits
FLITF registers
RM0090
Flash
memory
AHB
periph1
SRAM and
external
memories
AHB
periph2
MS30466V3