Power Control Registers (Stm32F405Xx/07Xx And Stm32F415Xx/17Xx); Pwr Power Control Register (Pwr_Cr); For Stm32F405Xx/07Xx And Stm32F415Xx/17Xx - ST STM32F405 Reference Manual

RM0090
5.4 Power control registers (STM32F405xx/07xx and
STM32F415xx/17xx)
5.4.1

PWR power control register (PWR_CR)

STM32F405xx/07xx and STM32F415xx/17xx
for
Address offset: 0x00
Reset value: 0x0000 4000 (reset by wakeup from Standby mode)
31 30 29
15 14 13
VOS
Res.
rw
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 VOS: Regulator voltage scaling output selection
Bits 13:10 Reserved, must be kept at reset value.
Bit 9 FPDS: Flash power-down in Stop mode
Bit 8 DBP: Disable backup domain write protection
In reset state, the RCC_BDCR register, the RTC registers (including the backup registers),
and the BRE bit of the PWR_CSR register, are protected against parasitic write access. This
bit must be set to enable write access to these registers.
Bits 7:5 PLS[2:0]: PVD level selection
These bits are written by software to select the voltage threshold detected by the Power
Voltage Detector
Note: Refer to the electrical characteristics of the datasheet for more details.
28 27 26 25
12 11 10 9
FPDS
Reserved
rw
This bit controls the main internal voltage regulator output voltage to achieve a trade-off
between performance and power consumption when the device does not operate at the
maximum frequency.
0: Scale 2 mode
1: Scale 1 mode (default value at reset)
When set, the Flash memory enters power-down mode when the device enters Stop mode.
This allows to achieve a lower consumption in stop mode but a longer restart time.
0: Flash memory not in power-down when the device is in Stop mode
1: Flash memory in power-down when the device is in Stop mode
0: Access to RTC and RTC Backup registers and backup SRAM disabled
1: Access to RTC and RTC Backup registers and backup SRAM enabled
000: 2.0 V
001: 2.1 V
010: 2.3 V
011: 2.5 V
100: 2.6 V
101: 2.7 V
110: 2.8 V
111: 2.9 V
24 23 22
Reserved
8 7 6
DBP PLS[2:0]
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RM0090 Rev 18
Power controller (PWR)
21 20 19 18
5 4 3 2
PVDE CSBF CWUF
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17 16
1 0
PDDS LPDS
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