Table 60. Dma2D Register Map And Reset Values - ST STM32F405 Reference Manual

RM0090
11.5.21 DMA2D register map
The following table summarizes the DMA2D registers. Refer to
for the DMA2D register base address.
Offset Register
DMA2D_CR
0x0000
Reset value
DMA2D_ISR
0x0004
Reset value
DMA2D_IFCR
0x0008
Reset value
DMA2D_FGMAR
0x000C
Reset value
DMA2D_FGOR
0x0010
Reset value
DMA2D_BGMAR
0x0014
Reset value
DMA2D_BGOR
0x0018
Reset value
DMA2D_FGPFCCR
0x001C
Reset value
DMA2D_FGCOLR
0x0020
Reset value
DMA2D_BGPFCCR
0x0024
Reset value
DMA2D_BGCOLR
0x0028
Reset value
DMA2D_FGCMAR
0x002C
Reset value
DMA2D_BGCMAR
0x0030
Reset value
DMA2D_OPFCCR
0x0034
Reset value
DMA2D_OCOLR
0x0038
Reset value
DMA2D_OMAR
0x003C
Reset value

Table 60. DMA2D register map and reset values

Reserved
0 0 0 0 0 0 0 0 0
Reserved
0 0 0 0 0 0 0 0 0
Reserved
ALPHA[7:0]
0 0 0 0 0 0 0 0
APLHA[7:0]
0 0 0 0 0 0 0 0 0
ALPHA[7:0]
0 0 0 0 0 0 0 0
APLHA[7:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
APLHA[7:0]
Reserved
Reserved
Reserved
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
Chrom-Art Accelerator™ controller (DMA2D)
Reserved
0 0
Reserved
Reserved
MA[31:0]
0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0
Reserved
0 0 0
RED[7:0]
0 0 0 0 0 0 0 0
Reserved
0 0 0
RED[7:0]
0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0
Reserved
RED[7:0]
A
ALPHA[3:0]
0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0
RM0090 Rev 18
Section 2.3: Memory map
0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
LO[13:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
LO[13:0]
0 0 0 0 0 0 0 0
CS[7:0]
Res
0 0 0 0 0 0 0
GREEN[7:0]
0 0 0 0 0 0 0 0 0
CS[7:0]
Res
0 0 0 0 0 0 0
GREEN[7:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
GREEN[7:0]
RED[4:0] GREEN[6:0]
RED[4:0] GREEN[4:0]
RED[3:0] GREEN[3:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
Reserved
0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
CM[3:0]
0 0 0 0 0 0
BLUE[7:0]
0 0 0 0 0 0
CM[3:0]
0 0 0 0 0 0
BLUE[7:0]
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
CM[2:0]
0 0 0
BLUE[7:0]
BLUE[4:0]
BLUE[4:0]
BLUE[3:0]
0 0 0 0 0 0
0 0 0 0 0 0
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