Figure 253. Txe/Rxne/Bsy Behavior In Master / Full-Duplex Mode; Rxonly=0) In Case Of Continuous Transfers - ST STM32F405 Reference Manual

RM0090
1. Enable the SPI by setting the SPE bit to 1.
2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE
flag).
3. Wait until TXE=1 and write the second data item to be transmitted. Then wait until
RXNE=1 and read the SPI_DR to get the first received data item (this clears the RXNE
bit). Repeat this operation for each data item to be transmitted/received until the n–1
received data.
4. Wait until RXNE=1 and read the last received data.
5. Wait until TXE=1 and then wait until BSY=0 before disabling the SPI.
This procedure can also be implemented using dedicated interrupt subroutines launched at
each rising edges of the RXNE or TXE flag.
Figure 253. TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and
Example in Master mode with CPOL=1, CPHA=1
SCK
MISO/MOSI (out)
TXE flag
Tx buffer
(write SPI_DR)
BSY flag
MISO/MOSI (in)
RXNE flag
Rx buffer
(read SPI_DR)
software software waits
writes 0xF1 until TXE=1 and
into SPI_DR writes 0xF2 into
SPI_DR

RXONLY=0) in case of continuous transfers

DATA1 = 0xF1
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
set by hardware
cleared by software
0xF1 0xF2
set by hardware
DATA 1 = 0xA1
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
set by hardware
software waits software waits
until RXNE=1 until TXE=1 and
and reads 0xA1 writes 0xF3 into
from SPI_DR SPI_DR
DATA2 = 0xF2
set by hardware
cleared by software
0xF3
DATA 2 = 0xA2
cleared by software
0xA1
software waits
until RXNE=1
and reads 0xA2
from SPI_ DR
RM0090 Rev 18
Serial peripheral interface (SPI)
DATA3 = 0xF3
set by hardware
DATA 3 = 0xA3
0xA2
software waits
until RXNE=1
and reads 0xA3
from SPI_DR
reset by hardware
0xA3
ai17343
887/1749
925