Rcc Ahb3 Peripheral Reset Register (Rcc_Ahb3Rstr); Rcc Apb1 Peripheral Reset Register (Rcc_Apb1Rstr) - ST STM32F405 Reference Manual

Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
6.3.7

RCC AHB3 peripheral reset register (RCC_AHB3RSTR)

Address offset: 0x18
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29
15 14 13
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 FMCRST: Flexible memory controller module reset
6.3.8

RCC APB1 peripheral reset register (RCC_APB1RSTR)

Address offset: 0x20
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29
UART8R UART7R PWR
DACRST
ST ST RST
rw rw rw
15 14 13
SPI3 SPI2
RST RST
Reserved
rw rw
174/1749
28 27 26 25
12 11 10 9
Set and cleared by software.
0: does not reset the FMC module
1: resets the FMC module
28 27 26 25
CAN2 CAN1
Reser-
RST RST
ved
rw rw
12 11 10 9
WWDG
RST
Reserved
rw
24 23 22
Reserved
8 7 6
Reserved
24 23 22
I2C3 I2C2
Reser-
RST RST
ved
rw rw
8 7 6
TIM14 TIM13 TIM12
RST RST RST
rw rw rw
RM0090 Rev 18
21 20 19 18
5 4 3 2
21 20 19 18
I2C1 UART5 UART4 UART3
RST RST RST RST
rw rw rw rw
5 4 3 2
TIM7 TIM6 TIM5 TIM4
RST RST RST RST
rw rw rw rw
RM0090
17 16
1 0
FMCRST
rw
17 16
UART2
Reser-
RST
ved
rw
1 0
TIM3 TIM2
RST RST
rw rw