ST STM32F405 Reference Manual page 671

RM0090
19.3.12 Timer synchronization (TIM9/12)
The TIM timers are linked together internally for timer synchronization or chaining. Refer to
Section 18.3.15: Timer synchronization
Note: The clock of the slave timer must be enabled prior to receive events from the master timer,
and must not be changed on-the-fly while triggers are received from the master timer.
19.3.13 Debug mode
When the microcontroller enters debug mode (Cortex
counter either continues to work normally or stops, depending on DBG_TIMx_STOP
configuration bit in DBG module. For more details, refer to
for timers, watchdog, bxCAN and I
General-purpose timers (TIM9 to TIM14)
for details.
®
2
C.
RM0090 Rev 18
-M4 with FPU core halted), the TIMx
Section 38.16.2: Debug support
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