Gpio Port Bit Set/Reset Register (Gpiox_Bsrr) (X = A; (X = A - ST STM32F405 Reference Manual

Hide thumbs Also See for STM32F405:

Table of Contents

General-purpose I/Os (GPIO)

GPIO port bit set/reset register (GPIOx_BSRR) (x = A..I/J/K)

Address offset: 0x18

Reset value: 0x0000 0000

Bits 31:16 BRy: Port x reset bit y (y = 0..15)

Note: If both BSx and BRx are set, BSx has priority.

Bits 15:0 BSy: Port x set bit y (y= 0..15)

GPIO port configuration lock register (GPIOx_LCKR)

(x = A..I/J/K)

This register is used to lock the configuration of the port bits when a correct write sequence

is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the

GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the

LOCK sequence has been applied on a port bit, the value of this port bit can no longer be

modified until the next MCU or peripheral reset.

A specific write sequence is used to write to the GPIOx_LCKR register. Only word access

(32-bit long) is allowed during this write sequence.

Each lock bit freezes a specific configuration register (control and alternate function

Address offset: 0x1C

Reset value: 0x0000 0000

Access: 32-bit word only, read/write register

These bits are write-only and can be accessed in word, half-word or byte mode. A read to

these bits returns the value 0x0000.

0: No action on the corresponding ODRx bit

1: Resets the corresponding ODRx bit

These bits are write-only and can be accessed in word, half-word or byte mode. A read to

these bits returns the value 0x0000.

0: No action on the corresponding ODRx bit

1: Sets the corresponding ODRx bit

RM0090 Rev 18

Chapters

Table of Contents

Do you have a question about the STM32F405 and is the answer not in the manual?