I-Bus; D-Bus; S-Bus; Figure 2. System Architecture For Stm32F42Xxx And Stm32F43Xxx Devices - ST STM32F405 Reference Manual

Memory and bus architecture

Figure 2. System architecture for STM32F42xxx and STM32F43xxx devices

ARM
64-Kbyte
Cortex-M4
CCM data RAM
2.1.1

I-bus

This bus connects the Instruction bus of the Cortex
This bus is used by the core to fetch instructions. The target of this bus is a memory
containing code (internal Flash memory/SRAM or external memories through the
FSMC/FMC).
2.1.2

D-bus

This bus connects the databus of the Cortex
to the BusMatrix. This bus is used by the core for literal load and debug access. The target
of this bus is a memory containing code or data (internal Flash memory or external
memories through the FSMC/FMC).
2.1.3

S-bus

This bus connects the system bus of the Cortex
bus is used to access data located in a peripheral or in SRAM. Instructions may also be
fetched on this bus (less efficient than ICode). The targets of this bus are the internal
SRAM1, SRAM2 and SRAM3, the AHB1 peripherals including the APB peripherals, the
AHB2 peripherals and the external memories through the FSMC/FMC.
62/1749
GP
GP
DMA1
DMA2
Bus matrix-S
RM0090 Rev 18
MAC
USB OTG
LCD-TFT
Ethernet
HS
®
-M4 with FPU core to the BusMatrix.
®
-M4 with FPU to the 64-Kbyte CCM data RAM
®
-M4 with FPU core to a BusMatrix. This
Chrom ART Accelerator
(DMA2D)
ICODE
Flash
memory
DCODE
SRAM1
112 Kbyte
SRAM2
16 Kbyte
SRAM3
64 Kbyte
AHB2
peripherals
AHB1
peripherals
FMC external
MemCtl
RM0090
APB1
APB2
MS30421V6