ST STM32F405 Reference Manual page 334

DMA controller (DMA)
Bits 5:3 FS[2:0]: FIFO status
Bit 2 DMDIS: Direct mode disable
Bits 1:0 FTH[1:0]: FIFO threshold selection
334/1749
These bits are read-only.
000: 0 < fifo_level < 1/4
001: 1/4 ≤ fifo_level < 1/2
010: 1/2 ≤ fifo_level < 3/4
011: 3/4 ≤ fifo_level < full
100: FIFO is empty
101: FIFO is full
others: no meaning
These bits are not relevant in the direct mode (DMDIS bit is zero).
This bit is set and cleared by software. It can be set by hardware.
0: Direct mode enabled
1: Direct mode disabled
This bit is protected and can be written only if EN is '0'.
This bit is set by hardware if the memory-to-memory mode is selected (DIR bit in
DMA_SxCR are "10") and the EN bit in the DMA_SxCR register is '1' because the direct
mode is not allowed in the memory-to-memory configuration.
These bits are set and cleared by software.
00: 1/4 full FIFO
01: 1/2 full FIFO
10: 3/4 full FIFO
11: full FIFO
These bits are not used in the direct mode when the DMIS value is zero.
These bits are protected and can be written only if EN is '0'.
RM0090 Rev 18
RM0090