ST STM32F405 Reference Manual page 355

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DMA2D interrupt flag clear register (DMA2D_IFCR)

Address offset: 0x0008

Reset value: 0x0000 0000

Bits 31:6 Reserved, must be kept at reset value

Bit 5 CCEIF: Clear configuration error interrupt flag

Bit 4 CCTCIF: Clear CLUT transfer complete interrupt flag

Bit 3 CAECIF: Clear CLUT access error interrupt flag

Bit 2 CTWIF: Clear transfer watermark interrupt flag

Bit 1 CTCIF: Clear transfer complete interrupt flag

Bit 0 CTEIF: Clear Transfer error interrupt flag

Programming this bit to 1 clears the CEIF flag in the DMA2D_ISR register

Programming this bit to 1 clears the CTCIF flag in the DMA2D_ISR register

Programming this bit to 1 clears the CAEIF flag in the DMA2D_ISR register

Programming this bit to 1 clears the TWIF flag in the DMA2D_ISR register

Programming this bit to 1 clears the TCIF flag in the DMA2D_ISR register

Programming this bit to 1 clears the TEIF flag in the DMA2D_ISR register

RM0090 Rev 18

Chrom-Art Accelerator™ controller (DMA2D)

CCTCIF CAECIF

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