Figure 246. Spi Block Diagram - ST STM32F405 Reference Manual

Serial peripheral interface (SPI)
28.3 SPI functional description
28.3.1 General description
The block diagram of the SPI is shown in
MOSI
MISO
SCK
NSS
Usually, the SPI is connected to external devices through four pins:
•
MISO: Master In / Slave Out data. This pin can be used to transmit data in slave mode
and receive data in master mode.
•
MOSI: Master Out / Slave In data. This pin can be used to transmit data in master
mode and receive data in slave mode.
•
SCK: Serial Clock output for SPI masters and input for SPI slaves.
• NSS: Slave select. This is an optional pin to select a slave device. This pin acts as a
'chip select' to let the SPI master communicate with slaves individually and to avoid
contention on the data lines. Slave NSS inputs can be driven by standard IO ports on
the master device. The NSS pin may also be used as an output if enabled (SSOE bit)
and driven low if the SPI is in master configuration. In this manner, all NSS pins from
devices connected to the Master NSS pin see a low level and become slaves when
they are configured in NSS hardware mode. When configured in master mode with
NSS configured as an input (MSTR=1 and SSOE=0) and if NSS is pulled low, the SPI
enters the master mode fault state: the MSTR bit is automatically cleared and the
device is configured in slave mode (refer to
A basic example of interconnections between a single master and a single slave is
illustrated in
876/1749

Figure 246. SPI block diagram

Read
Rx buffer
Shift register
Tx buffer
Write
Baud rate generator
Master control logic
Figure 247.
RM0090 Rev 18
Figure 246.
Address and data bus
SPI_CR2
TXE RXNE
IE
LSB first
SPI_SR
BSY
Communication control
BR[2:0]
LSB
SPE
FIRST
BIDI BIDI
MODE OE
Section
ERR TXDM
0 0 SSOE
IE IE
MOD CRC
OVR 0 0
F ERR
BR2 BR1 BR0 MSTR CPOL
SPI_CR1
CRC RX
CRCEN DFF SSM
Next ONLY
28.3.10).
RM0090
RXDM
AEN AEN
TXE RXNE
0
1
CPHA
SSI
MS51604V1