Figure 150. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36; Figure 151. Counter Timing Diagram, Internal Clock Divided By N - ST STM32F405 Reference Manual

General-purpose timers (TIM2 to TIM5)

Figure 150. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

Counter overflow (cnt_ovf)
Update interrupt flag (UIF)
1. Center-aligned mode 2 or 3 is used with an UIF on overflow.
600/1749
CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register
Update event (UEV)

Figure 151. Counter timing diagram, internal clock divided by N

CK_INT
Timerclock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
0034 0035
20 1F
RM0090 Rev 18
0036 0035
01 00
RM0090
MS37344V1
MS37345V1