Slowing Down System Clocks; Peripheral Clock Gating; Table 23. Low-Power Mode Summary - ST STM32F405 Reference Manual

Power controller (PWR)
Only enabled NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.
Mode name Entry
WFI or Return
Sleep
from ISR
(Sleep now or
Sleep-on-
WFE
exit)
PDDS and LPDS
bits +
Stop SLEEPDEEP bit
+ WFI, Return
from ISR or WFE
PDDS bit +
SLEEPDEEP bit
Standby
+ WFI, Return
from ISR or WFE
5.3.1

Slowing down system clocks

In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be
reduced by programming the prescaler registers. These prescalers can also be used to slow
down peripherals before entering Sleep mode.
For more details refer to
5.3.2

Peripheral clock gating

In Run mode, the HCLKx and PCLKx for individual peripherals and memories can be
stopped at any time to reduce power consumption.
To further reduce power consumption in Sleep mode the peripheral clocks can be disabled
prior to executing the WFI or WFE instructions.
128/1749

Table 23. Low-power mode summary

Wakeup
Any interrupt
Wakeup event
Any EXTI line (configured
in the EXTI registers,
internal and external lines)
WKUP pin rising edge,
RTC alarm (Alarm A or
Alarm B), RTC Wakeup
event, RTC tamper
events, RTC time stamp
event, external reset in
NRST pin, IWDG reset
Section 7.3.3: RCC clock configuration register
RM0090 Rev 18
Effect on
Effect on 1.2 V V
DD
domain clocks domain
clocks
CPU CLK OFF
no effect on other
None
clocks or analog
clock sources
HSI and
All 1.2 V domain HSE
clocks OFF oscillator
s OFF
RM0090
Voltage regulator
ON
ON or in low- power
mode (depends on
PWR power control
register (PWR_CR)
for
STM32F405xx/07x
x and
STM32F415xx/17x
x and PWR power
control register
(PWR_CR) for
STM32F405xx/07x
x and
STM32F415xx/17x
xPWR power
control register
(PWR_CR) for
STM32F42xxx and
STM32F43xxx
OFF
(RCC_CFGR).