ST STM32F405 Reference Manual page 350

Chrom-Art Accelerator™ controller (DMA2D)
The wrong configurations that can be detected are listed below:
•
Foreground CLUT automatic loading: MA bits of DMA2D_FGCMAR not aligned with
CCM of DMA2D_FGPFCCR.
•
Background CLUT automatic loading: MA of DMA2D_BGCMAR not aligned with CCM
of DMA2D_BGPFCCR
•
Memory transfer (except in register-to-memory mode): MA of DMA2D_FGMAR not
aligned with CM of DMA2D_FGPFCCR
•
Memory transfer (except in register-to-memory mode): CM in DMA2D_FGPFCCR are
invalid
•
Memory transfer (except in register-to-memory mode): PL bits of DMA2D_NLR odd
while CM of DMA2D_FGPFCCR is A4 or L4
•
Memory transfer (except in register-to-memory mode): LO bits in DMA2D_FGOR odd
while CM of DMA2D_FGPFCCR is A4 or L4
•
Memory transfer (only in blending mode): MA bits in DMA2D_BGMAR are not aligned
with the CM of DMA2D_BGPFCCR
•
Memory transfer: CM of DMA2D_BGPFCCR invalid (only in blending mode)
•
Memory transfer (only in blending mode): PL bits of DMA2D_NLR odd while CM of
DMA2D_BGPFCCR is A4 or L4
• Memory transfer (only in blending mode): LO bits of DMA2D_BGOR odd while CM of
DMA2D_BGPFCCR is A4 or L4
•
Memory transfer (except in memory to memory mode): MA bits in DMA2D_OMAR are
not aligned with CM bits in DMA2D_OPFCCR.
•
Memory transfer (except in memory to memory mode): CM bits in DMA2D_OPFCCR
invalid
•
Memory transfer: NL bits in DMA2D_NLR = 0
•
Memory transfer: PL bits in DMA2D_NLR = 0
11.3.12 DMA2D transfer control (start, suspend, abort and completion)
Once the DMA2D is configured, the transfer can be launched by setting the START bit of the
DMA2D_CR register. Once the transfer is completed, the START bit is automatically reset
and the TCIF flag of the DMA2D_ISR register is raised. An interrupt can be generated if the
TCIE bit of the DMA2D_CR is set.
The user application can suspend the DMA2D at any time by setting the SUSP bit of the
DMA2D_CR register. The transaction can then be aborted by setting the ABORT bit of the
DMA2D_CR register or can be restarted by resetting the SUSP bit of the DMA2D_CR
register.
The user application can abort at any time an ongoing transaction by setting the ABORT bit
of the DMA2D_CR register. In this case, the TCIF flag is not raised.
Automatic CLUT transfers can also be aborted or suspended by using the ABORT or the
SUSP bit of the DMA2D_CR register.
350/1749 RM0090 Rev 18
RM0090