ST STM32F405 Reference Manual page 501

RM0090
Bits 31:16: CXPOS[15:0]: Current X Position
Bits 15:0 CYPOS[15:0]: Current Y Position
16.7.13 LTDC Current Display Status Register (LTDC_CDSR)
This register returns the status of the current display phase which is controlled by the
HSYNC, VSYNC, and Horizontal/Vertical DE signals.
Example: if the current display phase is the vertical synchronization, the VSYNCS bit is set
(active high). If the current display phase is the horizontal synchronization, the HSYNCS bit
is active high.
Address offset: 0x48
Reset value: 0x0000 000F
31 30 29 28
15 14 13 12
Bits 31:24 Reserved, must be kept at reset value
Bit 3 HSYNCS: Horizontal Synchronization display Status
Bit 2 VSYNCS: Vertical Synchronization display Status
Bit 1 HDES: Horizontal Data Enable display Status
Bit 0 VDES: Vertical Data Enable display Status
Note: The returned status does not depend on the configured polarity in the LTDC_GCR register,
instead it returns the current active display phase.
These bits return the current X position
These bits return the current Y position
27 26 25
11 10 9
Reserved
0: Active low
1: Active high
0: Active low
1: Active high
0: Active low
1: Active high
0: Active low
1: Active high
RM0090 Rev 18
24 23 22 21
Reserved
8 7 6 5
LCD-TFT controller (LTDC)
20 19 18 17
4 3 2 1
HSYNC VSYNC
HDES
S S
r r r
16
0
VDES
r
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