ST STM32F405 Reference Manual page 239

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RM0090
Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGRST: Window watchdog reset
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 TIM14RST: TIM14 reset
Bit 7 TIM13RST: TIM13 reset
Bit 6 TIM12RST: TIM12 reset
Bit 5 TIM7RST: TIM7 reset
Bit 4 TIM6RST: TIM6 reset
Bit 3 TIM5RST: TIM5 reset
Bit 2 TIM4RST: TIM4 reset
Bit 1 TIM3RST: TIM3 reset
Bit 0 TIM2RST: TIM2 reset
Set and cleared by software.
0: does not reset the window watchdog
1: resets the window watchdog
Set and cleared by software.
0: does not reset TIM14
1: resets TIM14
Set and cleared by software.
0: does not reset TIM13
1: resets TIM13
Set and cleared by software.
0: does not reset TIM12
1: resets TIM12
Set and cleared by software.
0: does not reset TIM7
1: resets TIM7
Set and cleared by software.
0: does not reset TIM6
1: resets TIM6
Set and cleared by software.
0: does not reset TIM5
1: resets TIM5
Set and cleared by software.
0: does not reset TIM4
1: resets TIM4
Set and cleared by software.
0: does not reset TIM3
1: resets TIM3
Set and cleared by software.
0: does not reset TIM2
1: resets TIM2
RM0090 Rev 18
239/1749
266

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