Rcc Ahb1 Peripheral Reset Register (Rcc_Ahb1Rstr) - ST STM32F405 Reference Manual

RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)
Bit 2 HSIRDYF: HSI ready interrupt flag
Bit 1 LSERDYF: LSE ready interrupt flag
Bit 0 LSIRDYF: LSI ready interrupt flag
7.3.5

RCC AHB1 peripheral reset register (RCC_AHB1RSTR)

Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29 28
OTGH
S
Reserved
RST
rw
15 14 13 12
CRCR
ST
Reserved
rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 OTGHSRST: USB OTG HS module reset
Bits 28:26 Reserved, must be kept at reset value.
Bit 25 ETHMACRST: Ethernet MAC reset
Bits 24:23 Reserved, must be kept at reset value.
Set by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is
set.
Cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the HSI oscillator
1: Clock ready interrupt caused by the HSI oscillator
Set by hardware when the External Low Speed clock becomes stable and LSERDYDIE is
set.
Cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the LSE oscillator
1: Clock ready interrupt caused by the LSE oscillator
Set by hardware when the internal low speed clock becomes stable and LSIRDYDIE is set.
Cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the LSI oscillator
1: Clock ready interrupt caused by the LSI oscillator
27 26 25
ETHMAC
RST
Reserved
rw
11 10 9
Reserved
Set and cleared by software.
0: does not reset the USB OTG HS module
1: resets the USB OTG HS module
Set and cleared by software.
0: does not reset Ethernet MAC
1: resets Ethernet MAC
24 23 22
DMA2
RST
Reserved
rw
8 7 6
GPIOI GPIOH GPIOGG GPIOF
RST RST RST
rw rw rw
RM0090 Rev 18
21 20 19 18
DMA1
RST
Reserved
rw
5 4 3 2
GPIOE GPIOD GPIOC
RST RST RST RST
rw rw rw rw
17 16
1 0
GPIOB GPIOA
RST RST
rw rw
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