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Memory and bus architecture
Figure 1. System architecture for STM32F405xx/07xx and STM32F415xx/17xx devices
64-Kbyte
Cortex-M4
CCM data RAM
60/1749
ARM
GP
DMA1
Bus matrix-S
GP
MAC
USB OTG
DMA2
Ethernet
HS
RM0090 Rev 18
ICODE
Flash
memory
DCODE
SRAM1
112 Kbyte
SRAM2
16 Kbyte
AHB1
peripherals
AHB2
peripherals
FSMC
Static MemCtl
RM0090
APB1
APB2
ai18490d
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