Figure 236. Hash Interrupt Mapping Diagram - ST STM32F405 Reference Manual

Hash processor (HASH)
25.3.8 HASH interrupt
There are two individual maskable interrupt sources generated by the HASH processor.
They are connected to the same interrupt vector.
You can enable or disable the interrupt sources individually by changing the mask bits in the
HASH_IMR register. Setting the appropriate mask bit to 1 enables the interrupt.
The status of the individual interrupt sources can be read from the HASH_SR register.
25.4 HASH registers
The HASH core is associated with several control and status registers and five message
digest registers.
All these registers are accessible through word accesses only, else an AHB error is
generated.
25.4.1 HASH control register (HASH_CR) for STM32F415/417xx
Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
15 14 13
DINNE
Reserved
Bits 31:17 Reserved, forced by hardware to 0.
Bits 15:13 Reserved, forced by hardware to 0.
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Figure 236. HASH interrupt mapping diagram

DCIS
DCIM
DINIS
DINIM
28 27 26 25
12 11 10 9
NBW
r r r r
Bit 16 LKEY: Long key selection
This bit selects between short key (≤ 64 bytes) or long key (> 64 bytes) in HMAC
mode
0: Short key (≤ 64 bytes)
1: Long key (> 64 bytes)
Note: This selection is only taken into account when the INIT bit is set and MODE
= 1. Changing this bit during a computation has no effect.
24 23 22
Reserved
8 7 6
ALGO[0] MODE
r rw rw
RM0090 Rev 18
HASH interrupt to NVIC
21 20 19 18
5 4 3 2
DATATYPE DMAE INIT
rw rw rw w
RM0090
ai16086
17 16
LKEY
rw
1 0
Reserved