Table 52. Supported Color Mode In Input - ST STM32F405 Reference Manual

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Chrom-Art Accelerator™ controller (DMA2D)

They are programmed through a set of control registers:

DMA2D foreground memory address register (DMA2D_FGMAR)

DMA2D foreground offset register (DMA2D_FGOR)

DMA2D background memory address register (DMA2D_BGMAR)

DMA2D background offset register (DMA2D_BGBOR)

DMA2D number of lines register (number of lines and pixel per lines) (DMA2D_NLR)

When the DMA2D operates in register-to-memory mode, none of the FIFOs is activated.

When the DMA2D operates in memory-to-memory mode (no pixel format conversion nor

blending operation), only the FG FIFO is activated and acts as a buffer.

When the DMA2D operates in memory-to-memory operation with pixel format conversion

(no blending operation), the BG FIFO is not activated.

DMA2D foreground and background pixel format converter (PFC)

DMA2D foreground pixel format converter (PFC) and background pixel format converter

perform the pixel format conversion to generate a 32-bit per pixel value. The PFC can also

modify the alpha channel.

The first stage of the converter converts the color format. The original color format of the

foreground pixel and background pixels are configured through the CM[3:0] bits of the

DMA2D_FGPFCCR and DMA2D_BGPFCCR, respectively.

The supported input formats are given in

Table 52. Supported color mode in input

RM0090 Rev 18

Table 52: Supported color mode in

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