Figure 160. Capture/Compare Channel 1 Main Circuit; Figure 161. Output Stage Of Capture/Compare Channel (Channel 1) - ST STM32F405 Reference Manual

General-purpose timers (TIM2 to TIM5)
Read CCR1H
S
read_in_progress
Read CCR1L
R
Input
CC1S[1]
mode
CC1S[0]
IC1PS
CC1E
CC1G
TIMx_EGR
TIMx_CNT > TIMx_CCR1
TIMx_CNT = TIMx_CCR1
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
606/1749

Figure 160. Capture/compare channel 1 main circuit

APB Bus
MCU-peripheral interface
8
Capture/compare preload register
capture_transfer
Capture /compare shadow register
Capture
Counter

Figure 161. Output stage of capture/compare channel (channel 1)

ETRF
Output mode
controller
OC1M[2:0]
TIM x_CCMR1
RM0090 Rev 18
8
write_in_progress
compare_transfer
Comparator
To the master mode
controller
oc1ref
write CCR1H
S
write CCR1L
R
Output
CC1S[1]
mode
CC1S[0]
OC1PE
UEV
(from time
base unit)
CNT>CCR1
CNT=CCR1
0
Output
Enable
Circuit
1
CC1P
TIMx_CCER
CC1E
TIMx_CCER
RM0090
OC1PE
TIMx_CCMR1
MS33144V1
OC1
ai17187b