Power Control Registers (Stm32F42Xxx And Stm32F43Xxx); Pwr Power Control Register (Pwr_Cr); For Stm32F42Xxx And Stm32F43Xxx - ST STM32F405 Reference Manual

Power controller (PWR)
5.5

Power control registers (STM32F42xxx and STM32F43xxx)

5.5.1

PWR power control register (PWR_CR)

for STM32F42xxx and STM32F43xxx

Address offset: 0x00
Reset value: 0x0000 C000 (reset by wakeup from Standby mode)
31 30 29
15 14 13
VOS[1:0] ADCDC1
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Bits 31:20 Reserved, must be kept at reset value.
Bits 19:18 UDEN[1:0]: Under-drive enable in stop mode
Bit 17 ODSWEN: Over-drive switching enabled.
Note: On any over-drive switch (enabled or disabled), the system clock will be stalled during
Bit 16 ODEN: Over-drive enable
144/1749
28 27 26
Reserved
12 11 10
MRUDS LPUDS FPDS
Res.
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These bits are set by software. They allow to achieve a lower power consumption in Stop
mode but with a longer wakeup time.
When set, the digital area has less leakage consumption when the device enters Stop mode.
00: Under-drive disable
01: Reserved
10: Reserved
11:Under-drive enable
This bit is set by software. It is cleared automatically by hardware after exiting from Stop
mode or when the ODEN bit is reset. When set, It is used to switch to Over-drive mode.
To set or reset the ODSWEN bit, the HSI or HSE must be selected as system clock.
The ODSWEN bit must only be set when the ODRDY flag is set to switch to Over-drive
mode.
0: Over-drive switching disabled
1: Over-drive switching enable
the internal voltage set up.
This bit is set by software. It is cleared automatically by hardware after exiting from Stop
mode. It is used to enabled the Over-drive mode in order to reach a higher frequency.
To set or reset the ODEN bit, the HSI or HSE must be selected as system clock. When the
ODEN bit is set, the application must first wait for the Over-drive ready flag (ODRDY) to be
set before setting the ODSWEN bit.
0: Over-drive disabled
1: Over-drive enabled
25 24 23 22
9 8 7 6
DBP PLS[2:0]
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d
RM0090 Rev 18
21 20 19 18
UDEN[1:0]
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5 4 3 2
PVDE CSBF CWUF
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RM0090
17 16
ODSWE
ODEN
N
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1 0
PDDS LPDS
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