Figure 281. Audio Sampling Frequency Definition; Figure 282. I - ST STM32F405 Reference Manual

Serial peripheral interface (SPI)
When the master mode is configured, a specific action needs to be taken to properly
program the linear divider in order to communicate with the desired audio frequency.
I²SxCLK
1. Where x could be 2 or 3.
Figure 281
performance, the I2SxCLK clock source can be either the PLLI2S output (through R division
factor) or an external clock (mapped to I2S_CKIN pin).
The audio sampling frequency can be 192 kHz, 96 kHz, or 48 kHz. In order to reach the
desired frequency, the linear divider needs to be programmed according to the formulas
below:
When the master clock is generated (MCKOE in the SPI_I2SPR register is set):
F = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16-bit wide
S
F = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD)*4)] when the channel frame is 32-bit wide
S
When the master clock is disabled (MCKOE bit cleared):
F = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16-bit wide
S
F = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD))] when the channel frame is 32-bit wide
S
Table 127
Note: Other configurations are possible that allow optimum clock precision.
908/1749

Figure 281. Audio sampling frequency definition

16-or 32-bit left
sampling point
F : audio sampling frequency
S

Figure 282. I

8-bit linear divider
+ reshaping stage
I²SDIV[7:0]
MCKOE ODD
presents the communication clock architecture. To achieve high-quality audio
provides example precision values for different clock configurations.
16-or 32-bit
right channel
channel
32- or 64-bits
F
S
2
S clock generator architecture
Divider by 4
RM0090 Rev 18
sampling point
0
0
Div2
1
1
MCKOE
RM0090
MS30108V1
MCK
CK
MS30109V1