Figure 276. Operations Required To Receive 0X3478Ae; Figure 277. Lsb Justified 16-Bit Extended To 32-Bit Packet Frame With Cpol = 0; Figure 278. Example Of Lsb Justified 16-Bit Extended To 32-Bit Packet Frame - ST STM32F405 Reference Manual

Serial peripheral interface (SPI)

Figure 277. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0

CK
WS
SD
When 16-bit data frame extended to 32-bit channel frame is selected during the I
configuration phase, Only one access to SPI_DR is required. The 16 remaining bits are
forced by hardware to 0x0000 to extend the data to 32-bit format. In this case it corresponds
to the half-word MSB.
If the data to transmit or the received data are 0x76A3 (0x0000 76A3 extended to 32-bit),
the operation shown in

Figure 278. Example of LSB justified 16-bit extended to 32-bit packet frame

In transmission mode, when TXE is asserted, the application has to write the data to be
transmitted (in this case 0x76A3). The 0x000 field is transmitted first (extension on 32-bit).
TXE is asserted again as soon as the effective data (0x76A3) is sent on SD.
In reception mode, RXNE is asserted as soon as the significant half-word is received (and
not the 0x0000 field).
In this way, more time is provided between two write or read operations to prevent underrun
or overrun conditions.
906/1749

Figure 276. Operations required to receive 0x3478AE

First read from Data register
conditioned by RXNE=1
0xXX34
Only the 8 LSB of the
half-word are significant.
A field of 0x00 is forced
instead of the 8 MSBs.
16-bit data
0 forced
MSB
Channel left 32-bit
Figure 278 is required.
Only one access to the SPIx-DR register
RM0090 Rev 18
Second read from Data register
conditioned by RXNE=1
0x78AE
Reception
Transmission
16-bit remaining
LSB
0x76A3
RM0090
MS19597V1
Channel right
MS30105V1
2
S
MS19598V1