ST STM32F405 Reference Manual page 166

Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
Bits 22:21 MCO1: Microcontroller clock output 1
Bits 20:16 RTCPRE: HSE division factor for RTC clock
Caution: The software has to set these bits correctly to ensure that the clock supplied to the
Bits 15:13 PPRE2: APB high-speed prescaler (APB2)
Caution: The software has to set these bits correctly not to exceed 90 MHz on this domain.
Bits 12:10 PPRE1: APB Low speed prescaler (APB1)
Caution: The software has to set these bits correctly not to exceed 45 MHz on this domain.
Bits 9:8 Reserved, must be kept at reset value.
166/1749
Set and cleared by software. Clock source selection may generate glitches on MCO1. It is
highly recommended to configure these bits only after reset before enabling the external
oscillators and PLL.
00: HSI clock selected
01: LSE oscillator selected
10: HSE oscillator clock selected
11: PLL clock selected
Set and cleared by software to divide the HSE clock input clock to generate a 1 MHz clock
for RTC.
RTC is 1 MHz. These bits must be configured if needed before selecting the RTC
clock source.
00000: no clock
00001: no clock
00010: HSE/2
00011: HSE/3
00100: HSE/4
...
11110: HSE/30
11111: HSE/31
Set and cleared by software to control APB high-speed clock division factor.
The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after
PPRE2 write.
0xx: AHB clock not divided
100: AHB clock divided by 2
101: AHB clock divided by 4
110: AHB clock divided by 8
111: AHB clock divided by 16
Set and cleared by software to control APB low-speed clock division factor.
The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after
PPRE1 write.
0xx: AHB clock not divided
100: AHB clock divided by 2
101: AHB clock divided by 4
110: AHB clock divided by 8
111: AHB clock divided by 16
RM0090 Rev 18
RM0090