Interrupts; Option Bytes; Description Of User Option Bytes; Table 13. Flash Interrupt Request - ST STM32F405 Reference Manual

Embedded Flash memory interface
1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register (BSY is active when erase/program operation is on going on bank
1 or bank 2)
2. Set the PG bit in the FLASH_CR register
3. Perform the data write operation(s) to the desired memory address inside main
memory block or OTP area
4. Wait for the BSY bit to be reset.
3.6.6

Interrupts

Setting the end of operation interrupt enable bit (EOPIE) in the FLASH_CR register enables
interrupt generation when an erase or program operation ends, that is when the busy bit
(BSY) in the FLASH_SR register is cleared (operation completed, correctly or not). In this
case, the end of operation (EOP) bit in the FLASH_SR register is set.
If an error occurs during a program, an erase, or a read operation request, one of the
following error flags is set in the FLASH_SR register:
•
PGAERR, PGPERR, PGSERR (Program error flags)
•
WRPERR (Protection error flag)
•
RDERR (Read protection error flag) for STM32F42xxx and STM32F43xxx devices
only.
In this case, if the error interrupt enable bit (ERRIE) is set in the FLASH_CR register, an
interrupt is generated and the operation error bit (OPERR) is set in the FLASH_SR register.
Note: If several successive errors are detected (for example, in case of DMA transfer to the Flash
memory), the error flags cannot be cleared until the end of the successive write requests.
Interrupt event
End of operation
Write protection error
Programming error
Read protection error
3.7

Option bytes

3.7.1

Description of user option bytes

The option bytes are configured by the end user depending on the application requirements.
Table 14
Address
0x1FFF C000
0x1FFF C008
88/1749

Table 13. Flash interrupt request

shows the organization of these bytes inside the user configuration sector.

Table 14. Option byte organization

[63:16]
Reserved
Reserved
Event flag
EOP
WRPERR
PGAERR, PGPERR, PGSERR
RDERR
ROP & user option bytes (RDP & USER)
SPRMOD and Write protection nWRP bits for
sectors 0 to 11
RM0090 Rev 18
RM0090
Enable control bit
EOPIE
ERRIE
ERRIE
ERRIE
[15:0]