ST STM32F405 Reference Manual page 367

RM0090
11.5.17 DMA2D output offset register (DMA2D_OOR)
Address offset: 0x0040
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Reserved
rw rw
Bits 31:14 Reserved, must be kept at reset value
Bits 13:0 LO[13: 0]: Line Offset
11.5.18 DMA2D number of line register (DMA2D_NLR)
Address offset: 0x0044
Reset value: 0x0000 0000
31 30 29 28
Reserved
rw rw
15 14 13 12
rw rw rw rw
Bits 31:30 Reserved, must be kept at reset value
Bits 29:16 PL[13: 0]: Pixel per lines
Bits 15:0 NL[15: 0]: Number of lines
27 26 25 24
11 10 9 8
rw rw rw rw
Line offset used for the output (expressed in pixels). This value is used for the address
generation. It is added at the end of each line to determine the starting address of the
next line. These bits can only be written when data transfers are disabled. Once the
transfer has started, they are read-only.
27 26 25 24
rw rw rw rw
11 10 9 8
rw rw rw rw
Number of pixels per lines of the area to be transferred. These bits can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.
If any of the input image format is 4-bit per pixel, pixel per lines must be even.
Number of lines of the area to be transferred. These bits can only be written when data
transfers are disabled. Once the transfer has started, they are read-only.
RM0090 Rev 18
Chrom-Art Accelerator™ controller (DMA2D)
23 22 21
Reserved
7 6 5
LO[13:0]
rw rw rw
23 22 21
PL[13:0]
rw rw rw
7 6 5
NL[15:0]
rw rw rw
20 19 18 17
4 3 2 1
rw rw rw rw
20 19 18 17
rw rw rw rw
4 3 2 1
rw rw rw rw
16
0
rw
16
rw
0
rw
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