Rcc Registers; Rcc Clock Control Register (Rcc_Cr) - ST STM32F405 Reference Manual

Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)
7.3

RCC registers

Refer to
register descriptions.
7.3.1

RCC clock control register (RCC_CR)

Address offset: 0x00
Reset value: 0x0000 XX83 where X is undefined.
Access: no wait state, word, half-word and byte access
31 30 29
Reserved
15 14 13
r r r
Bits 31:28 Reserved, must be kept at reset value.
Bit 27 PLLI2SRDY: PLLI2S clock ready flag
Bit 26 PLLI2SON: PLLI2S enable
Bit 25 PLLRDY: Main PLL (PLL) clock ready flag
Bit 24 PLLON: Main PLL (PLL) enable
Bits 23:20 Reserved, must be kept at reset value.
Bit 19 CSSON: Clock security system enable
224/1749
Section 1.1: List of abbreviations for registers
28 27 26 25
PLLI2S PLLI2S PLLRD
RDY ON Y
r rw r
12 11 10 9
HSICAL[7:0]
r r r r
Set by hardware to indicate that the PLLI2S is locked.
0: PLLI2S unlocked
1: PLLI2S locked
Set and cleared by software to enable PLLI2S.
Cleared by hardware when entering Stop or Standby mode.
0: PLLI2S OFF
1: PLLI2S ON
Set by hardware to indicate that PLL is locked.
0: PLL unlocked
1: PLL locked
Set and cleared by software to enable PLL.
Cleared by hardware when entering Stop or Standby mode. This bit cannot be reset if PLL
clock is used as the system clock.
0: PLL OFF
1: PLL ON
Set and cleared by software to enable the clock security system. When CSSON is set, the
clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by
hardware if an oscillator failure is detected.
0: Clock security system OFF (Clock detector OFF)
1: Clock security system ON (Clock detector ON if HSE oscillator is stable, OFF if not)
24 23 22
PLLON
Reserved
rw
8 7 6
HSITRIM[4:0]
r rw rw
RM0090 Rev 18
for a list of abbreviations used in
21 20 19 18
CSS HSE
ON BYP
rw rw
5 4 3 2
Res.
rw rw rw
RM0090
17 16
HSE HSE
RDY ON
r rw
1 0
HSI
HSION
RDY
r rw