Rcc Ahb1 Peripheral Clock Register (Rcc_Ahb1Enr) - ST STM32F405 Reference Manual

Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
6.3.10

RCC AHB1 peripheral clock register (RCC_AHB1ENR)

Address offset: 0x30
Reset value: 0x0010 0000
Access: no wait state, word, half-word and byte access.
31 30 29 28
OTGH
ETHM
S OTGH
ACPTP
Reser-
ULPIE SEN
EN
ved
N
rw rw rw
15 14 13 12
CRCE
N
Reserved
rw
Bit 31 Reserved, must be kept at reset value.
Bit 30 OTGHSULPIEN: USB OTG HSULPI clock enable
Bit 29 OTGHSEN: USB OTG HS clock enable
Bit 28 ETHMACPTPEN: Ethernet PTP clock enable
Bit 27 ETHMACRXEN: Ethernet Reception clock enable
Bit 26 ETHMACTXEN: Ethernet Transmission clock enable
Bit 25 ETHMACEN: Ethernet MAC clock enable
Bit 24 Reserved, must be kept at reset value.
Bit 23 DMA2DEN: DMA2D clock enable
180/1749
27 26 25
ETHM ETHM
ETHMA
ACRXE ACTXE
CEN
N N
rw rw rw
11 10 9
GPIOK GPIOJ
EN EN
Res.
rw rw
This bit is set and cleared by software. It must be cleared when the OTG_HS is used in FS
mode.
0: USB OTG HS ULPI clock disabled
1: USB OTG HS ULPI clock enabled
This bit is set and cleared by software.
0: USB OTG HS clock disabled
1: USB OTG HS clock enabled
This bit is set and cleared by software.
0: Ethernet PTP clock disabled
1: Ethernet PTP clock enabled
This bit is set and cleared by software.
0: Ethernet Reception clock disabled
1: Ethernet Reception clock enabled
This bit is set and cleared by software.
0: Ethernet Transmission clock disabled
1: Ethernet Transmission clock enabled
This bit is set and cleared by software.
0: Ethernet MAC clock disabled
1: Ethernet MAC clock enabled
This bit is set and cleared by software.
0: DMA2D clock disabled
1: DMA2D clock enabled
24 23 22
DMA2D DMA2E
EN N
Res.
rw rw
8 7 6
GPIOIE GPIOH GPIOG GPIOFE
N EN EN
rw rw rw
RM0090 Rev 18
21 20 19
DMA1E CCMDAT
Res.
N ARAMEN
rw
5 4 3
GPIOD
GPIOEEN
N EN
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RM0090
18 17 16
BKPSR
AMEN
Reserved
rw
2 1 0
GPIOC GPIO GPIO
EN BEN AEN
rw rw rw