Figure 118. Edge-Aligned Pwm Waveforms (Arr=8) - ST STM32F405 Reference Manual

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Advanced-control timers (TIM1 and TIM8)

compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR)

then OCxREF is held at '1'. If the compare value is 0 then OCxRef is held at '0'.

Downcounting configuration

Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to

Downcounting mode

In PWM mode 1, the reference signal OCxRef is low as long as

TIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is

greater than the auto-reload value in TIMx_ARR, then OCxREF is held at '1'. 0% PWM

is not possible in this mode.

PWM center-aligned mode

Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from

'00' (all the remaining configurations having the same effect on the OCxRef/OCx signals).

The compare flag is set when the counter counts up, when it counts down or both when it

counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the

shows some edge-aligned PWM waveforms in an example where

Figure 118. Edge-aligned PWM waveforms (ARR=8)

Counter register

RM0090 Rev 18

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