ST STM32F405 Reference Manual page 428

Analog-to-digital converter (ADC)
Bits 17:16 ADCPRE: ADC prescaler
Note: 00: PCLK2 divided by 2
Bits 15:14 DMA: Direct memory access mode for multi ADC mode
Bit 13 DDS: DMA disable selection (for multi-ADC mode)
Bit 12 Reserved, must be kept at reset value.
428/1749
Set and cleared by software to select the frequency of the clock to the ADC. The clock is
common for all the ADCs.
01: PCLK2 divided by 4
10: PCLK2 divided by 6
11: PCLK2 divided by 8
This bit-field is set and cleared by software. Refer to the DMA controller section for more
details.
00: DMA mode disabled
01: DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)
10: DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)
11: DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2)
This bit is set and cleared by software.
0: No new DMA request is issued after the last transfer (as configured in the DMA
controller). DMA bits are not cleared by hardware, however they must have been cleared
and set to the wanted mode by software before new DMA requests can be generated.
1: DMA requests are issued as long as data are converted and DMA = 01, 10 or 11.
RM0090 Rev 18
RM0090