ST STM32F405 Reference Manual page 874

Serial peripheral interface (SPI)
28.2 SPI and I
28.2.1 SPI features
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Full-duplex synchronous transfers on three lines
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Simplex synchronous transfers on two lines with or without a bidirectional data line
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8- or 16-bit transfer frame format selection
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Master or slave operation
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Multimaster mode capability
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8 master mode baud rate prescalers (f
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Slave mode frequency (f
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Faster communication for both master and slave
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NSS management by hardware or software for both master and slave: dynamic change
of master/slave operations
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Programmable clock polarity and phase
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Programmable data order with MSB-first or LSB-first shifting
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Dedicated transmission and reception flags with interrupt capability
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SPI bus busy status flag
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SPI TI mode
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Hardware CRC feature for reliable communication:
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–
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Master mode fault, overrun and CRC error flags with interrupt capability
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1-byte transmission and reception buffer with DMA capability: Tx and Rx requests
874/1749
2
S main features
PCLK
CRC value can be transmitted as last byte in Tx mode
Automatic CRC error checking for last received byte
/2 max.)
PCLK
/2 max)
RM0090 Rev 18
RM0090