ST STM32F405 Reference Manual page 104

Embedded Flash memory interface
Bit 31 LOCK: Lock
Write to 1 only. When it is set, this bit indicates that the FLASH_CR register is locked. It is
cleared by hardware after detecting the unlock sequence.
In the event of an unsuccessful unlock operation, this bit remains set until the next reset.
Bits 30:26 Reserved, must be kept cleared.
Bit 25 ERRIE: Error interrupt enable
This bit enables the interrupt generation when the OPERR bit in the FLASH_SR register is set
to 1.
Bit 24 EOPIE: End of operation interrupt enable
This bit enables the interrupt generation when the EOP bit in the FLASH_SR register goes to
1.
Bits 23:17 Reserved, must be kept cleared.
Bit 16 STRT: Start
This bit triggers an erase operation when set. It is set only by software and cleared when the
BSY bit is cleared.
Bits 15:10 Reserved, must be kept cleared.
Bits 9:8 PSIZE[1:0]: Program size
These bits select the program parallelism.
Bit 7 Reserved, must be kept cleared.
Bits 6:3 SNB[3:0]: Sector number
These bits select the sector to erase.
Bit 2 MER: Mass Erase
Erase activated for all user sectors.
Bit 1 SER: Sector Erase
Sector Erase activated.
Bit 0 PG: Programming
Flash programming activated.
104/1749
0: Error interrupt generation disabled
1: Error interrupt generation enabled
0: Interrupt generation disabled
1: Interrupt generation enabled
00 program x8
01 program x16
10 program x32
11 program x64
0000 sector 0
0001 sector 1
...
1011 sector 11
Others not allowed
RM0090 Rev 18
RM0090