Figure 148. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6; Figure 149. Counter Timing Diagram, Internal Clock Divided By 2 - ST STM32F405 Reference Manual

Hide thumbs Also See for STM32F405:

Table of Contents

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR register) is set (depending on the URS bit):

The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC

The auto-reload active register is updated with the preload value (content of the

TIMx_ARR register). Note that if the update source is a counter overflow, the auto-

reload is updated before the counter is reloaded, so that the next period is the expected

one (the counter is loaded with the new value).

The following figures show some examples of the counter behavior for different clock

frequencies.

Figure 148. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6

Update interrupt flag (UIF)

1. Here, center-aligned mode 1 is used, for more details refer to

Timerclock = CK_CNT

Counter register

Counter underflow

Counter overflow

Update event (UEV)

Timerclock = CK_CNT

Counter register

Counter underflow

Update event (UEV)

Update interrupt flag (UIF)

General-purpose timers (TIM2 to TIM5)

Section 18.4.1: TIMx control register 1 (TIMx_CR1)

RM0090 Rev 18

Table of Contents