Figure 240. I2C Block Diagram For Stm32F42X/43X - ST STM32F405 Reference Manual

RM0090
SDA
SCL
SMBA
1. SMBA is an optional signal in SMBus mode. This signal is not applicable if SMBus is disabled.
2
27.3.2 I C slave mode
By default the I
Master mode a Start condition generation is needed.
The peripheral input clock must be programmed in the I2C_CR2 register in order to
generate correct timings. The peripheral input clock frequency must be at least:
•
2 MHz in Sm mode
•
4 MHz in Fm mode
As soon as a start condition is detected, the address is received from the SDA line and sent
to the shift register. Then it is compared with the address of the interface (OAR1) and with
OAR2 (if ENDUAL=1) or the General Call address (if ENGC = 1).
Note: In 10-bit addressing mode, the comparison includes the header sequence (11110xx0),
where xx denotes the two most significant bits of the address.
2
Figure 240. I C block diagram for STM32F42x/43x
Data
Noise
control
filter
Clock
Noise
control
filter
Clock control
Register (CCR)
Control registers
(CR1&CR2)
Status registers
(SR1&SR2)
2
C interface operates in Slave mode. To switch from default Slave mode to
RM0090 Rev 18
Inter-integrated circuit (I2C) interface
Data register
Data shift register
Comparator
Own address register
Dual address register
PEC register
Control
logic
Interrupts DMA requests & ACK
PEC calculation
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