ST STM32F405 Reference Manual page 687

RM0090
19.5.2 TIM10/11/13/14 Interrupt enable register (TIMx_DIER)
Address offset: 0x0C
Reset value: 0x0000
15 14 13
Bits 15:2
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
Bit 0 UIE: Update interrupt enable
19.5.3 TIM10/11/13/14 status register (TIMx_SR)
Address offset: 0x10
Reset value: 0x0000
15 14 13
Reserved
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to '0'.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bits 8:2 Reserved, must be kept at reset value.
Bit 1 CC1IF: Capture/compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value. It is cleared by
software.
0: No match.
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit
goes high on the counter overflow.
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIMx_CCR1 register.
0: No input capture occurred.
1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected
on IC1 which matches the selected polarity).
12 11 10 9
Reserved
Reserved, must be kept at reset value.
0: CC1 interrupt disabled
1: CC1 interrupt enabled
0: Update interrupt disabled
1: Update interrupt enabled
12 11 10 9
CC1OF
rc_w0
General-purpose timers (TIM9 to TIM14)
8 7 6
8 7 6
Reserved
RM0090 Rev 18
5 4 3 2
5 4 3 2
1 0
CC1IE UIE
rw rw
1 0
CC1IF UIF
rc_w0 rc_w0
687/1749
695