Rcc Apb2 Peripheral Reset Register (Rcc_Apb2Rstr) - ST STM32F405 Reference Manual

Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)
7.3.9

RCC APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x24
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29
15 14 13
SPI1
SYSCF
Reser- G RST Reser-
RST
ved ved
rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 TIM11RST: TIM11 reset
Bit 17 TIM10RST: TIM10 reset
Bit 16 TIM9RST: TIM9 reset
Bit 15 Reserved, must be kept at reset value.
Bit 14 SYSCFGRST: System configuration controller reset
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1RST: SPI1 reset
Bit 11 SDIORST: SDIO reset
Bits 10:9 Reserved, must be kept at reset value.
240/1749
28 27 26 25
Reserved
12 11 10 9
SDIO
RST
Reserved
rw rw
Set and cleared by software.
0: does not reset TIM11
1: resets TIM14
Set and cleared by software.
0: does not reset TIM10
1: resets TIM10
Set and cleared by software.
0: does not reset TIM9
1: resets TIM9
Set and cleared by software.
0: does not reset the System configuration controller
1: resets the System configuration controller
Set and cleared by software.
0: does not reset SPI1
1: resets SPI1
Set and cleared by software.
0: does not reset the SDIO module
1: resets the SDIO module
24 23 22
8 7 6
USART
ADC
RST
Reserved
rw
RM0090 Rev 18
21 20 19 18
TIM11
RST
rw
5 4 3 2
USART
6 1
Reserved
RST RST
rw rw
RM0090
17 16
TIM10 TIM9
RST RST
rw rw
1 0
TIM8 TIM1
RST RST
rw rw