Figure 141. Counter Timing Diagram, Update Event When Arpe=0 (Timx_Arr Not Preloaded); Figure 142. Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded) - ST STM32F405 Reference Manual

RM0090
Figure 141. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not
Update interrupt flag (UIF)
Figure 142. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR
Update interrupt flag (UIF)
Auto-reload preload register
Auto-reload shadow register
Downcounting mode
In downcounting mode, the counter counts from the auto-reload value (content of the
TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a
counter underflow event.
An Update event can be generate at each counter underflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller)
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Auto-reload register
Write a new value in TIMx_ARR
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Write a new value in TIMx_ARR
General-purpose timers (TIM2 to TIM5)
preloaded)
31 32 33 34 35 36 00
FF
preloaded)
F0 F1 F2 F3 F4 F5 00
F5
F5
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01 02 03 04 05 06 07
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