ST STM32F405 Reference Manual page 384

Interrupts and events
12.3 registers
EXTI
Refer to
register descriptions.
12.3.1 Interrupt mask register (EXTI_IMR)
Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
15 14 13
MR15 MR14 MR13 MR12
rw rw rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 MRx: Interrupt mask on line x
12.3.2 Event mask register (EXTI_EMR)
Address offset: 0x04
Reset value: 0x0000 0000
31 30 29
15 14 13
MR15 MR14 MR13 MR12
rw rw rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 MRx: Event mask on line x
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Section 1.1: List of abbreviations for registers
28 27 26 25
Reserved
12 11 10 9
MR11 MR10 MR9
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0: Interrupt request from line x is masked
1: Interrupt request from line x is not masked
28 27 26 25
Reserved
12 11 10 9
MR11 MR10 MR9
rw rw rw rw
0: Event request from line x is masked
1: Event request from line x is not masked
24 23 22
MR22 MR21
rw
8 7 6
MR8 MR7 MR6
rw rw rw
24 23 22
MR22 MR21
rw
8 7 6
MR8 MR7 MR6
rw rw rw
RM0090 Rev 18
for a list of abbreviations used in
21 20 19 18
MR20 MR19 MR18
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5 4 3 2
MR5 MR4 MR3 MR2
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21 20 19 18
MR20 MR19 MR18
rw rw rw rw
5 4 3 2
MR5 MR4 MR3 MR2
rw rw rw rw
RM0090
17 16
MR17 MR16
rw rw
1 0
MR1 MR0
rw rw
17 16
MR17 MR16
rw rw
1 0
MR1 MR0
rw rw